Thierry Grandpierre
Noisy le grand
Bâtiment: Building: ESIEE
2 Bd Blaise Pascal$Cite Descartes Bp 99 Noisy le grand France
Bureau: Office: 5256
Thierry Grandpierre
Enseignant-Chercheur (HDR) à ESIEE (Ecole d'Ingénieurs de l'UGE)
Membre des équipes A3SI et LRT du Laboratoire d'Informatique Gaspard Monge (LIGM) - UMR 8049
Responsable de la 5ème année de la filière CyberSécurité (labélisée SecNumEdu par l'ANSSI) en temps plein (ingénieur FISE)
Responsable de la salle de réalité virtuelle ESIEE, de l'espace Texas Instrument de l'ESIEE.
Thèmes d'enseignement :
programmation C, architecture RISC scalaire, superscalaire, pipeline, microcontrôleurs (ARM Cortex M, MSP430, Atmega, ESP32), processeurs (Intel Core, Cortex A : iMx6, A53, A72 etc), programmation système Linux, programmation parallèle OpenMP, SSE/AVX, programmation GPU (CUDA), réseaux (routeurs Cisco, Firewall, Sockets)
Réalité virtuelle : développement Unity, Unreal Engine, casque Occulus, HTC Vive. Cave 3 écrans stéréoscopique.
Réalité virtuelle/Mixte : casque Hololens 1 et Hololens 2
Thèmes de recherche :
Adéquation Algorithme Architecture : implémentation d'algorithme temps réel (stricts et souples) sur architectures multicomposants. Prédiction de performances, heuristiques, génération automatique de code distribué.
Applications en traitement des images : compressions vidéo, filtrage, arbres des composantes connexes, Tone mapping
Application en synthèse d'image : implémentation de la BRDF mesurée dans Unity
Mes dernières références
My latest references
ListePublicationThierryGrandpierre
PublicationsListThierryGrandpierre
Adéquation Algorithme Architecture : Modélisations, Implémentations, Optimisations pour Applications Temps Réel Embarquées. Embedded Systems. Université Paris Est, 2024
Multi-Criteria Optimization of Distributed Real-Time Network Topologies. 2024 IEEE 27th International Symposium on Real-Time Distributed Computing (ISORC), May 2024, Tunis, Tunisia. pp.1-11
⟨10.1109/ISORC61049.2024.10551327⟩
Procédé de calcul d’un pire temps de transmission, programme d’ordinateur et système informatique associés. France, N° de brevet: 2312310 (n°de dépôt). 2023
A New Modelling Framework for Coarse-Grained Programmable Architectures. Compas 2020, Jun 2021, Lyon, France
Modelling and Mapping Framework for Coarse-GrainedProgrammable Architectures. 14th Summer School on Modelling and Verification of Parallel Processes, Jun 2020, (on-line), France
Visite virtuelle des salles blanches ESIEE. Journal sur l'enseignement des sciences et technologies de l'information et des systèmes, 2019, 18, pp.1002
⟨10.1051/j3ea/20191002⟩
A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures. 22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES 2019), May 2019, St Goar, Germany
⟨10.1145/3323439.3323982⟩
An hypervisor approach for mixed critical real-time UAV applications. 2019 IEEE International Conference on Pervasive Computing and Communications Workshops (PerCom Workshops), Mar 2019, Kyoto, France. pp.985-991
⟨10.1109/PERCOMW.2019.8730705⟩
A Mapping Methodology for Coarse-Grained Pipelined Configurable Architectures. 14th Workshop on Models and Algorithms for Planning and Scheduling Problems (MAPSP 2019), Jun 2019, Renesse, Netherlands
Dispositif médical en radiologie interventionnelle de guidage temps réel d'une aiguille médicale d'opération dans un volume. France, Patent n° : EP3682808A1. 2019, pp.15
A mapping tool for configurable pipeline co-processors. Colloque National du GDR SoC-SiP, GDR-SOC-SIP, Jun 2018, Paris, France
Embedded Real-Time H264/AVC High Definition Video Encoder on TI's KeyStone Multicore DSP. Journal of Signal Processing Systems, 2017, 86 (1), pp.67-84
⟨10.1007/s11265-015-1098-x⟩
Optimized Implementation of H.264/AVC Motion Estimation on a Mixed Architecture Using SynDEx-Mix. International Review on Computers and Software (IRECOS), 2016, 11 (5)
⟨10.15866/irecos.v11i5.8764⟩
Real-time H264/AVC high definition video encoder on a multicore DSP TMS320C6678. 2015 International Conference on Computer Vision and Image Analysis Applications (ICCVIA), Jan 2015, Sousse, Tunisia
⟨10.1109/ICCVIA.2015.7351893⟩
GPU Implementation of Linear Morphological Openings with Arbitrary Angle. Journal of Real-Time Image Processing, 2015, 10 (1), pp.27-41
⟨10.1007/s11554-012-0248-7⟩
GOP level parallelism implementation for real-time H264/AVC video encoder on multicore DSP TMS320C6472. EDERC 2014, IEEE, EURASIP, Nov 2014, Milan, Italy. pp.152-156
⟨10.1109/EDERC.2014.6924378⟩
Automatic Hardware/Software interface generation for SynDEx-mixte. ATSIP 2014, Mar 2014, Sousse, Tunisia. pp.512-516
⟨10.1109/ATSIP.2014.6834668⟩
GOP level parallelism implementation for real-time H264/AVC video encoder on multicore DSP TMS320C6472. 2014 6th European Embedded Design in Education and Research Conference (EDERC), Sep 2014, Milano, France
⟨10.1109/EDERC.2014.6924378⟩
Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera. Journal of Real-Time Image Processing, 2014, 12, pp.791-812
⟨10.1007/s11554-014-0470-6⟩
Optimizations for real-time implementation of H264/AVC video encoder on DSP processor. International Review on Computers and Software (IRECOS), 2013, 8 (9), pp.2025-2035
Optimisations structurelles et matérielles de l'encodeur vidéo H264/AVC sur un seul coeur d'un DSP multicoeurs TMS320C6472. GRETSI 2013 (Symposium on Signal and Image Processing), 2013, BREST, France
Optimisations structurelles et matérielles de l'encodeur vidéo H264/AVC sur un seul coeur d'un DSP multicoeurs TMS320C6472. gretsi, Sep 2013, Brest, France
Dispositif et procédé de projection d'images sur des écrans mobiles. France, Patent n° : FR2991787A1. 2012, pp.18
Real Time Dynamic Tone-Mapping Operator on GPU. Journal of Real-Time Image Processing, 2012, 7 (3), pp.165-172
Accelerometer and Magnetometer Based Gyroscope Emulation on Smart Sensor for a Virtual Reality Application. Sensors & Transducers., 2012, 14-1 (Special Issue ISSN 1726-5479), p32-p47
Real-time H.264/AVC baseline decoder implementation on TMS320C6416. Journal of Real-Time Image Processing, 2012, 7 (4), pp.215-232
⟨10.1007/s11554-010-0181-6⟩
Learning System for Defactorization Factor Classification of Factorized Data Dependence Graph. IJACT : International Journal of Advancements in Computing Technology, 2011, 3 (4), pp.1-13
Latency and power optimization in AAA methodology for integrated circuits. ICECS 2010, IEEE, Dec 2010, Athens, Greece. pp.639-642
⟨10.1109/ICECS.2010.5724593⟩
Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices. Neural Computing and Applications, 2009, ? (ISSN 0941-0643), 10pp
Mabasa, Mohamed Akil, Thierry Grandpierre, B.J. van Wyk, M.A. van Wyk. Automatic VHDL Code Generation for Fuzzy Logic Systems. African Journal of Science and Technology, 2008, ? (1), 10pp
Parallel Algorithm for Concurrent Computation of Connected Component Tree. Advanced Concepts for Intelligent Vision Systems (ACIVS'08), Oct 2008, France. pp.230-241
AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable Circuits. International Embedded Systems Symposium, 2007, France. 10pp
Implementing Real-Time Algorithms by using the AAA Prototyping Methodology. ?. Embedded System Design, Techniques and Trends, 231, Springer, pp.27-36, 2007, IFIP
Saouli, Mohamed Akil, Thierry Grandpierre. Load Balancing and Static Placement/Scheduling Heuristic on Distributed Heterogeneous Architecture. International Review on Computers and Software (IRECOS), 2007, ? (1), pp.227-234
FPGA-based architecture for hardware compression/decompression of wide format images. Journal of Real-Time Image Processing, 2006, 1 (2), pp.163-170
A rapid prototyping methodology to implement and optimizing image processing algorithms for FPGAs. IS&T / SPIE, Symposium on Electronic Imaging Science and Technologies, Real-Time Imaging IX Conference, 2006, San Jose, USA, France. 10pp
A methodology to implement real-time applications on reconfigurable circuits. Journal of Supercomputing, 2004, 30 (3), pp.283-301
⟨10.1023/B:SUPE.0000045213.82276.8e⟩
A methodology to implement real-time applications on reconfigurable circuits. Special issue on Engineering of Configurable Systems of the Journal of Supercomputing, 2004, 30 (1), pp.283-301
From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs Transformations. Field Programmable Logic and Application, 13th International Conference, Sep 2003, Lisbon, Portugal. pp.934-943
⟨10.1007/978-3-540-45234-8_90⟩
From Algorithm and Architecture Specifications to Automatic Generation of Distributed Real-Time Executives: a Seamless Flow of Graphs Transformations. 2003 1st IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2003), Jun 2003, Mont Saint Michel, France
⟨10.1109/MEMCOD.2003.1210097⟩
A joystick driving algorithm with a collision stop feature on an electric vehicle (Cycab). IEEE Intelligent Vehicle Symposium 2002, Jun 2002, Versailles, France. pp.501-506
⟨10.1109/IVS.2002.1188000⟩
PROMPT : A mapping environment for telecom applications on System on a Chip. International conference on Compilers, architecture, and synthesis for embedded systems, Nov 2000, San Jose, United States. pp.41-47
⟨10.1145/354880.354887⟩
Optimized Rapid Prototyping for Real-Time Embedded Heterogeneous Multiprocessors. the seventh international workshop, 1999, Rome, France
⟨10.1145/301177.301489⟩